NAND flash memory, a typical nonvolatile semiconductor storage, has been conventionally configured by a matrix aligned NAND cell units. A NAND cell unit comprises a first select gate transistor electrically connected to a bit line, a second select gate transistor electrically connected to a source line, and electrically readable, writable and erasable memory cell transistors which are each connected to a corresponding word line and disposed between the first and the second select gate transistors.
Memory device configured by such NAND cell unit is subject to requirement for high-density data storage and such requirement can be met by increasing the number of memory cell transistors connected in series. NAND flash memory executes an erase verify process after an erase operation to improve data reliability as disclosed in JP 2006-54036 A. However, as the number of memory cell transistors in a NAND cell unit is increased for densification, reliability of erase verify is in turn reduced. Such trade off may be explained by the following.
Erase verification is evaluated by the voltage level detected at the bit line. In detecting the voltage level at the bit line, when constant voltage is applied on each of the word lines while a positive voltage for erase verification is applied on the source line, voltage drop occurring at source/drain of each of the memory cell transistors causes drop in potential of back bias from the source line side to the bit line side of the memory cell transistors. This results in variance in erase verify bias between the memory cell transistors, and thus, making it difficult to perform uniform verification across the memory cell transistors spanning from the source line side to the bit line side.
The above is especially true when the number of memory cell transistors connected between the first and the second select gate transistors are increased. As opposed to this, the technical concept disclosed in JP 2006-54036 A carries out a first and second erase verify operations where the first erase verify operation is carried out under the first bias and the second erase verify operation is carried out under the second bias which differs from the first bias. Such configuration, however, produces poor erase verify speed.